1. Field of the Invention
The present invention relates to a PLL (Phase Lock Loop) circuit for locking a carrier frequency at an accurate frequency. More particularly, the present invention relates to a PLL circuit configured to execute digital control on a DCO (Digitally Controlled Oscillator).
To put it in detail, the present invention relates to a PLL circuit for stabilizing a loop thereof without substantially increasing the number of bits of output by a phase comparator employed therein. In particular, the present invention relates to a PLL circuit for reducing a loop error and improving responsiveness of convergence by properly controlling the gain of the loop.
2. Description of the Related Art
In order to lock a carrier frequency at an accurate frequency in a radio communication terminal, the radio communication terminal is provided with a PLL (Phase Lock Loop) circuit. In the data-communication and satellite-communication fields, a large number of digital PLL circuits are used and serve as a subject of aggressive research. Such a digital PLL circuit includes a phase comparator having a digital configuration, a low-pass filter and a VCO (Voltage-Controlled Oscillator).
A typical digital PLL circuit includes the digital phase comparator, the low-pass filter and the voltage-controlled oscillator, which are connected to each other to form a loop. The digital phase comparator carries out an operation for comparing the phase of a reference signal with the phase of a signal outputted by the voltage-controlled oscillator, generating a voltage according to the difference in phase between the signals so as to reduce the phase difference, and changing the oscillation frequency of the signal outputted by the voltage-controlled oscillator. An in-synchronization state is defined as a state in which the phase difference detected by the digital phase comparator is zero or a close to zero. A lead-in state is defined as a state of transition from an out-of-synchronization state to an in-synchronization state. For more information, refer to Japanese Patent Laid-open No. Hei 8-148994 (Paragraph 0002, FIG. 14). It is to be noted that the low-pass filter is not only for removing components each having a high frequency from the signal outputted by the phase comparator in order to produce a smoothed direct current signal, but also for determining the synchronization and response characteristics of the PLL circuit. In addition, the low-pass filter also determines the loop gain in accordance with setting such as a cutoff frequency. Thus, the low-pass filter is an important component for the stability of the synchronized-phase state and for the time which is required to lead-in.
Most existing digital PLL circuits are each implemented as a hybrid PLL IC (integrated circuit), in which all PLL-circuit components except the voltage-controlled oscillator is integrated with digital circuits, that is, a digital circuit and an analog circuit coexist therein. The phase comparator here is a digital phase comparator consists of logic circuits. The phase comparator outputs a signal in one of three states by adoption of a charge-pump technique. Since the phase comparator consumes a voltage VDS between the drain and source in order to operate the comparator linearly; therefore the digital phase comparator is improper for a circuit system driven by a low voltage.
With semiconductor-process miniaturization going on in recent years, a PLL circuit having a full digital configuration has been attracting attention. In such circuit, a VCO controlled by an analog voltage is replaced with a DCO (Digitally Controlled Oscillator). FIG. 7 is a diagram showing a typical configuration of an all-digital PLL circuit employing a DCO. In the figure, a TDC (Time-to-Digital Converter) circuit converts a time difference corresponding to the fractional part of a dividing ratio into a digital value while an accumulator circuit converts the integer part into a digital value. The digital values corresponding to the dividing ratio thus detected are fed-back by a variety of techniques in order to digitally control. For more information, refer to R. B. Staszewski et al., All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13 μm CMOS (ISSCC 2004 Digest).
In the phase comparison process carried out by the digital PLL circuit of this type, in each period of a reference signal, it is performed a subtraction process of finding a difference between a digital value obtained by converting the dividing ratio and a digital value representing each cumulative addition value of a clock count expressed in a decimal-point format representing the oscillation frequency. For this reason, the variation range of the phase comparison process is limited by the number of bits. Thus, a phase comparison process carried out in a domain beyond the variation range becomes inaccurate, making the loop of the digital PLL circuit unstable. In addition, if the DCO is controlled by using a digital value representing a fractional dividing ratio obtained by dividing an oscillation frequency by a reference frequency, the loop gain will be equal to a ratio of a value output by the phase comparator to the fractional dividing ratio. Thus, in an attempt made to increase the loop gain in order to reduce an error generated in the closed loop, it is necessary to increase the number of bits expressing a value output by the phase comparator.
In addition, if the loop gain is set at a large value, the response time to a state of convergence becomes longer. Thus, in order to attain a state of convergence with a high degree of precision within a short time period required by each radio system, in a system making use of a negative feedback, the loop gain is generally switched from a value to another. To put it concretely, at an initial stage, the loop gain is set at a relatively small value but, as a process of convergence is carried forward thereafter, the loop gain is changed from the relatively small value to a larger value. In this case, however, there is raised a problem that, when the loop gain is changed from the relatively small value to the larger value, a discontinuity of the loop gain is generated, resulting in a delayed state of convergence. In order to solve this problem, there has been proposed a method for switching the loop gain as shown in a diagram of FIG. 8. For more information, refer to U.S. Pat. No. 6,851,492, and Chapter entitled “Frequency Synthesizers in Nanometer CMOS” of a text called ISSCC 2007 Short Course on Analog, Mixed-Signal and RF Circuit Design in Nanometer CMOS. In a configuration shown in the figure, however, even though assurance of the continuity of φE at a switching time is taken into consideration, the bit count output by an adder must be made greater than the bit count generated by a phase comparator in order to obtain a large loop gain.